The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device technique, particularly to a technique effective when adapted to a method for manufacturing a semiconductor device having an inlaid interconnect containing a main conductor film comprised mainly of copper and such a semiconductor device.
An inlaid interconnect structure is formed by embedding a wiring material in an interconnect opening such as interconnect trench or hole formed in an insulating film in accordance with a metallization technique called “damascene technique” (single damascene and dual damascene techniques). When copper is employed as a main wiring material, however, it easily diffuses in an insulating film compared with a metal such as aluminum. Diffusion of copper from an inlaid interconnect to an insulating film is therefore suppressed or prevented by covering the surfaces (bottom surface and side surfaces) of the inlaid interconnect made of copper with a thin barrier metal film so as to avoid direct contact of the inlaid interconnect with the insulating film. Alternatively, diffusion of copper from the upper surface of the inlaid interconnect to the insulating film is suppressed or prevented by forming an interconnect capping insulating film made of, for example, silicon nitride film over the upper surface of the insulating film having an interconnect opening formed therein and covering therewith the upper surface of the inlaid interconnect.
A damascene metallization technique is described, for example, in Japanese Patent Laid-Open No. 2000-323479 in which in an inlaid interconnect structure, a copper interconnect and an insulating film are formed to have different surface height. In Japanese Patent Laid-Open No. 111843/1999, disclosed is an inlaid interconnect structure obtained by forming, in an inlaid interconnect, a copper layer to have an upper surface level lower than that of an insulating film and then embedding a barrier insulating film in the resulting indented portion. In Japanese Patent Laid-Open No. 50632/1998, disclosed is an inlaid interconnect structure by lowering the upper surface level of each of the copper layer and barrier metal of the inlaid interconnect relative to that of the insulating film and embedding a barrier insulating film in the indented portion. In Japanese Patent Laid-Open No. 2000-277612, disclosed is a technique of preventing remaining of a slurry after CMP (chemical mechanical polishing) by forming the upper surface level of each of the barrier metal and metal film of an inlaid interconnect higher than that of the insulating film. In Japanese Patent Laid-Open No. 189602/1998, disclosed is a technique of forming the upper surface level of a tungsten plug a little higher than that of an insulating film and rounding an inlaid plug.